Overcoming 400G measurement challenges

Created September 5, 2019
Product Focus

The rapid worldwide growth in cloud computing is driving massive demand for high-performance datacenter infrastructure. To keep pace with this relentless demand, developers are transitioning to 400G technologies enabling smaller, faster, lower cost-per-bit solutions.

There are several core technologies that are enabling 400G, including the use of higher order modulation and higher data rates up to 56 GBaud. This new modulation scheme provides four-level pulse amplitude modulation (PAM4), which transmits two bits per symbol, doubling the data rate compared to conventional NRZ.

PAM4 signals, having a lower signal-to-noise ratio and 1/3 of the amplitude of equivalent NRZ, require more advanced tools and features for successful validation.

Figure 1

Figure 1 compares simple, baseband, NRZ (non-return to zero) signal modulation to the more bandwidth efficient PAM4 (4-level pulse amplitude modulation).

PAM4 cuts the bandwidth for a given data rate in half by transmitting two bits in each symbol, as indicated by Figure 1. With two bits per symbol, we must distinguish the data or bit rate, Gb/s, from the symbol or baud rate, GBd.

The abbreviation NRZ has been used informally to describe intuitive high/low signaling, but the formal description is 2-level pulse amplitude modulation, or PAM2. Since PAM4 signals do not return to zero after each symbol, they are also an NRZ signaling scheme.

The eye diagrams in Figure 1 indicate how the multiple symbol levels make PAM4 more sensitive to amplitude noise than PAM2-NRZ is. While PAM4 signals also suffer greater ISI (inter-symbol interference) than PAM2-NRZ at a given baud rate, they suffer much less at the same data rate. PAM4’s greater resilience to ISI at a given data rate on lossy electrical channels like backplanes is the primary reason for switching from PAM2NRZ. A close look at Figure 1 also reveals that increments in the signal levels do not consistently correspond to increments in the binary values of the PAM4 symbols; we’ll see why in Section 2.3.

For optical systems, the motivations to switch from NRZ-PAM2 to PAM4 include lowering the cost, improving power efficiencies, and the continuing challenge of seamless optical to electrical signal conversion.

PAM4 signal analysis borrows a great deal from the jitter and noise analysis developed for PAM2-NRZ by applying them separately to PAM4’s three-eye diagrams but also introduces new techniques to account for the interrelationships among the three eyes and to optimize conflicting and interdependent design parameters.

There are several techniques available for evaluating PAM4 technologies, however the emphasis must always be on the performance requirements that enable SerDes and transceivers to operate and interoperate in PAM4 systems.

https://uk.tek.com/document/application-note/pam4-signaling-high-speed-serial-technology-test-analysis-and-debug

In advancing beyond 25 Gb/s, high-speed serial data technology crossed an inflection point. For many applications, the technical advances that enabled multi-gigabit electrical data rates with PAM2-NRZ signal modulation can no longer economically produce the signal integrity required for reliable data transfer.

Development of PAM4 has led to new techniques to account for PAM4 signal properties like the relative orientation and proportions of the three eye diagrams.

Predicting the future of PAM4 designs and compliance criteria is precarious, but the introduction of requirements on parameters like TDECQ, SNDR, and COM that combine multiple measurements into figures of merit indicate that we’re moving away from strict requirements on quantities that can be measured in one step. Using figures of merit to balance interdependent quantities allows designers to optimize the performance of transceivers, SerDes, and channels in different ways.

Receiver technology, especially the use of elaborate CR, CTLE, and DFE internal circuitry, is changing rapidly and our test and measurement equipment is changing with it. As we advance beyond lane rates of 112 Gb/s to 200+ Gb/s, PAM4 transceivers will have to decode each of the three eye diagrams independently. We’re already seeing PAM4 receivers that integrate the roles of clock recovery and equalization into symbol decoding DSP algorithms that train their parameters on power up and can adapt as conditions change.

The Tektronix DPO70000SX 70 GHz bandwidth real-time oscilloscopes with appropriate O/E convertors—DPO7OE1 with 33 GHz bandwidth or DPO7OE2 with 59 GHz bandwidth—have the lowest noise in the industry and the flexibility to emulate the filtering, clock recovery, and receiver equalization requirements of both optical and electrical reference receivers, set up as shown in figure 2 below.

Figure 2

The tools and measurement considerations  needed  to analyze PAM4 signals, evaluate transmitters, and calibrate stressed receiver sensitivity, jitter, and tolerance tests and discussed in more technical  detail – https://uk.tek.com/wired-communications.

With the rapid development of several emerging core technologies that are enabling PAM4 in 400G/200G/100G/50G networks, including the use of higher order modulation and higher data rates, engineers are being continuingly confronted with new measurement challenges and standards – to assist in breaking down the complexity Tektronix have developed the ‘PAM4 in 400G/200G/100G/50G Networking Technology Poster’. I encourage every engineer to download – happy reading!

 

https://uk.tek.com/document/poster/pam4-400g-200g-100g-50g-networking-technology-poster

Dean Miles Head of Technical Marketing Tektronix EMEA

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This article was written
by Dean Miles