ECOC 2019: Anritsu to demonstrate 116-Gbps PAM4 error detector

Created September 4, 2019
Technologies and Products

Test equipment manufacturer Anritsu, will demonstrate its new PAM4 Error Detector module for its Signal Quality Analyser-R MP1900A Series PAM4 BERT on booth #28, at the ECOC Exhibition 2019 in Dublin, Ireland, from September 23 to 25 September 2019. With what the company claims is the world’s highest operation bit rate and Rx sensitivity, this new ED module supports high-accuracy Bit and Symbol Error Ratio measurement of PAM4 signals when combined with the previously released PAM4 Pattern Signal Generator.

Communications data traffic volumes are expected to grow with the spread of next generation 5G mobile communications and cloud computing services. As a result, data centres supporting fast, large-capacity communications are examining speed increases to 400GbE using four 53.125-Gbaud PAM4 lanes as well as future upgrades to 800GbE using eight PAM4 lanes.

Since the PAM4 method expresses 2 bits of data with four amplitude levels, it has one-third the signal level difference of the NRZ method using two levels, thus requiring instruments to have much higher input sensitivity performance, to evaluate signal quality (integrity). Moreover, at faster speeds, it is no longer possible to ignore the effects of losses from components, such as PC boards, cables, connectors in the transmission path, on measured results. As a consequence, evaluating the true performance of the devices under test requires not only excellent fundamental performance such as sensitivity and frequency bandwidth, but also high-level integrated functions, such as Clock Recovery and Equaliser, to compensate for the impact of losses. Anritsu developed this new Error Detector with built-in clock recovery and equaliser functions, to implement the highest sensitivity performance for PAM4 BER measurements.

The new PAM4 ED module uses a unique InP (Indium phosphide compound) semiconductor Rx circuit to achieve a sensitivity performance of 50 mV (typ.) for a 58-Gbaud PAM4 input. The built-in clock recovery and equaliser functions, and transmission path compensation, support validation of BER measurement results. As an additional value in the market, multichannel signal generation, combined with FEC patterns emulation and jitter tolerance testing, enables accurate evaluation of the true performance of optical transceiver modules and devices, as well as specification margins, in real life working conditions.

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This article was written
by Peter Dykes

Peter Dykes is a independent telecoms and technology journalist who has over that last 30 years written for a wide range of B2B publications and companies. A former BT engineer, he specialises in networks and associated support systems. He is currently Editor of Optical Connections.