High-Performance Coherent in CMOS: Foundational technology for WDM Optical Networking

Created September 5, 2018
Technical Features


• Optical networks continue to evolve with greater performance and flexibility based on a foundation of CMOS chip designs as fourth generation designs are under way
• Techniques to advance performance in spectral efficiency pave the way for a fourth generation of coherent optical DSP chips
• Optimisation of low-level circuits optimises designs for power efficiency
• The path forward for a fifth generation of coherent optical chip designs with respect to process technology must be carefully considered

The road to a fourth generation of coherent optical semiconductor chips

As the optical networking industry is ramping up on third generation coherent technology (defined as coherent DSPs supporting 55 – 69Gbaud 1), a fourth generation of developments are in the pipeline. It is worth considering the foundational technology which underpins these generations and the design challenges faced in realising these high-performance semiconductor devices. A decade ago, the first coherent transceiver CMOS chips were deployed for 40Gbps systems, paving the way for 100Gbps coherent WDM technology deployments in 2010. Successive generations doubled the optical line rate transmitted per wavelength from a single coherent chip each time.

These advancements in chip-level system design have helped drive the industry’s ability to deploy higher fibre capacities and, in turn, lowered the cost/bit for data transport. As well, successive coherent chip generations from some vendors allowed network operators to build greater flexibility in provisioning of services from their fibre plants. These devices delivered not just higher top end capacity of the optical line rate, but also a broad range of selectable line rates from a single device. The options for scaling and improving cost efficiency of networks changed radically over the last year with the release of systems based on programmable third generation coherent chips providing the ability to tune capacity to address all applications with a single design. Fourth generation devices are in design phase with the goal to continue the charge for greater fibre data capacities and more flexible networks.

Figure 1: Programmable capacity


Designing for spectral efficiency

The fourth generation of chips will continue to rely on the use of advanced Digital Signal Processing (DSP) including the use of more complex modulation formats (more bits/symbol) allowing greater data transmission capacity (more bits/s) for a given signal processing rate (baud or symbol/sec) through to the optical fibre. Minimising the increase in baud from generation to generation has allowed the use of lower bandwidth photonics and sub-components while gaining greater data throughput. This helps to reduce chip design constraints and minimises the system cost. For example, coherent CMOS devices have quadrupled in capacity going from 100Gbps to 400Gbps, but the baud (signal processing rate) has only had to double resulting in better spectral efficiency on the fibre. This trend will continue in future devices.

Figure 2: Spectral efficiency


As data rates per wavelength continue to increase, DSP techniques for mitigating the impact of non-linearities in the photonic components connecting coherent chips to the fibre, as well as dynamic non-linear responses due to transmission fibre medium such as cross-phase modulation and self-phase modulation, are vital to extract fractions of dB and maximise system performance.

Other elements of the coherent chip will affect the spectral efficiency of the optical system. The high-performance, high-speed Analogue-to-Digital Converters (ADCs) and Digital-to-Analogue Converters (DACs) drive signals to the optical line side of the DSP converter to and from the digital logic at the heart of the chip. They interface with the analogue electrical output of the photonic components which, in turn, modulate and demodulate the optical signal on the fibre and convert from photonic to electronic signals. Enhancing the analogue bandwidth of the ADCs and DACs mitigates noise and distortion inherent in all chip-level circuits and contributes to higher spectral efficiency of the optical system. In addition to maximising transmission performance, chip-level digital and analogue design considerations play a role in optimising for power dissipation.

Designing for power efficiency

CMOS chips for high performance computing-such as machine learning or data analytics-or those for mobile platforms-have intermittent off-state functions. In these types of designs, techniques such as power gating or power islands can be used; effectively powering off parts of the chip while not in use or in standby mode. Conversely, coherent optical devices are 100% in-service or ‘always-on’ devices. Since virtually all functions of these devices are continually operating, other power-saving techniques are more applicable such as clock gating and efficient clock routing. Given the extremely high data throughput of coherent DSPs, this translates to high frequency synchronisation signals. Carefully managing the design and distribution of the clock circuits will optimise for power efficiency.

And what does the future hold beyond a fourth generation?

State-of the-art for semiconductor design is ‘7nm’ CMOS which has moved to volume production in 2018 from some CMOS foundries. Fourth generation coherent optical chips developed in this process node will benefit from higher transistor density and lower power dissipation compared to the previous node. However, design implementation of chips starts to become significantly more challenging due to the finer geometries of the CMOS structures in 7nm and the constraints they impose on the physical layout of the chip.

Figure 3: FinFET transistor


As the wider semiconductor industry moves forward to introduce the next process node, currently termed ‘5 nm’, the motivation for doing designs in this node, for any application, will once again be for greater density and functionality within the same area or the same functionality in a much smaller chip area with lower power. But the gains in lower power dissipation with each CMOS node are reducing by an incremental amount. For coherent DSP devices, chip developers must weigh the return of lower power against the even greater challenges for design robustness and significantly higher costs to develop in 5nm.

1 “Third Generation Coherent Technology”, Andrew Schmitt, Cignal AI, July 25, 2018

Written by Patricia Bower, on behalf of Ciena.

Article posted Optical Connections News Team.