EZchip redefines the role of the network processor

Created January 23, 2013
Technologies and Products

EZchip Semiconductor has announced a class of network processor capable of performing traditional data plane processing as well as higher layer networking tasks.

“It [the device family] is designed to provide processing for all the networking layers, from layer two all the way to layer seven,” said Amir Eyal, EZChip’s vice president of business development. “In the past, network processors have offered layer-two to layer-three processing only.”
 
The device family, called the network processor for smart networks (NPS), is being aimed at Carrier Ethernet edge router platforms – the traditional telecom application for network processors – and data centre tasks such as security, load balancing and software-defined networking (SDN).
 
The NPS is also C-programmable whereas NPUs have traditionally be programmed using an assembly language or micro-code. “C-programmability and the Linux or similar operating system are a must-have because the [Layer 7] processing is so complex.”  
 
Using an NPS processor will eliminate the need for equipment service line cards that use general-purpose processors. More NPS-based cards can use the vacated line-card slots to boost the platform’s overall packet-processing performance. 
 
EZchip has announced the first two NPS devices: The NPS-200 and the more capable NPS-400. The NPS-400 is a 200Gbps duplex chip, giving it twice the packet-processing performance of EZchip’s latest NP-5 NPU.
 
NPS-400 comprises 256 CTOPs (C-programmable task-optimised processors), each capable of processing 16 threads. The device also includes an on-chip traffic manager. EZchip says up to eight NPS chips could be put on a line card, to achieve a 1.6Tbps packet throughput.
 
The first NPS samples will appear at the end of 2013, with NPS-based products deployed in 2015. Meanwhile, EZchip says it is sampling its NP-5 NPU this quarter.
 
By Roy Rubenstein
 
See Also: 

Press release: EZchip introduces NPS, a new breed of C-programmable NPU that enables the next wave of high-performance smart carrier and data-center networks

Microprocessor Report: EZchip breaks the NPU mold

Gazettabyte: Network processors to support multiple 100 Gigabit flows

Roy Rubenstein

This article was written
by Roy Rubenstein

is the editor of gazettabyte.com and has been researching and writing about the telecom and semiconductor industries for over 20 years.